1. Field of the Invention
The present invention relates generally to a bipolar transistor and, more particularly, to a method for forming a bipolar transistor with a raised extrinsic base in an integrated bipolar and complementary metal oxide semiconductor (BiCMOS) transistor circuit.
2. Background of the Invention
Bipolar transistors are electronic devices with two p-n junctions that are in close proximity to each other. A typical bipolar transistor has three device regions: an emitter, a collector, and a base disposed between the emitter and the collector. Ideally, the two p-n junctions, i.e., the emitter-base and collector-base junctions, are in a single layer of semiconductor material separated by a specific distance. Modulation of the current flow in one p-n junction by changing the bias of the nearby junction is called xe2x80x9cbipolar-transistor action.xe2x80x9d
If the emitter and collector are doped n-type and the base is doped p-type, the device is an xe2x80x9cnpnxe2x80x9d transistor. Alternatively, if the opposite doping configuration is used, the device is a xe2x80x9cpnpxe2x80x9d transistor. Because the mobility of minority carriers, i.e., electrons, in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher-frequency operation and higher-speed performances can be obtained with npn transistor devices. Therefore, npn transistors comprise the majority of bipolar transistors used to build integrated circuits.
As the vertical dimensions of the bipolar transistor are scaled more and more, serious device operational limitations have been encountered. One actively studied approach to overcome these limitations is to build transistors with emitter materials whose band gaps are larger than the band gaps of the material used in the base. Such structures are called heterojunction transistors.
Heterostructures comprising heterojunctions can be used for both majority carrier and minority carrier devices. Among majority carrier devices, heterojunction bipolar transistors (HBTs) in which the emitter is formed of silicon (Si) and the base of a silicon-germanium (SiGe) alloy have recently been developed. The SiGe alloy (often expressed simply as silicon-germanium) is narrower in band gap than silicon.
The advanced silicon-germanium bipolar and complementary metal oxide semiconductor (BiCMOS) technology uses a SiGe base in the heterojunction bipolar transistor. In the high-frequency (such as multi-GHz ) regime, conventional compound semiconductors such as GaAs and InP currently dominate the market for high-speed wired and wireless communications. SiCe BiCMOS promises not only a comparable performance to GaAs in devices such as power amplifiers, but also a substantial cost reduction due to the integration of heterojunction bipolar transistors with standard CMOS, yielding the so-called xe2x80x9csystem on a chip.xe2x80x9d
For high-performance HBT fabrication, yielding SiGe/Si HBTs, a conventional way to reduce the base resistance is through ion implantation into the extrinsic base. The ion implantation will cause damage, however, to the base region. Such damage may ultimately lead to degradation in device performance.
To avoid the implantation damage, a raised extrinsic base (Rext) is formed by depositing an extra layer of polycrystalline silicon (or SiGe) atop the conventional SiGe extrinsic base layer. There are essentially two processes that may be utilized to achieve such a raised extrinsic base. The first process involves selective epitaxy; the other involves chemical-mechanical polishing (CMP).
In a typical selective epitaxy process, the raised extrinsic base polycrystalline silicon is formed before the deposition of the intrinsic base SiGe. The intrinsic base SiGe is deposited selectively onto the exposed surface of silicon and polycrystalline silicon inside an over-hanging cavity structure. The selective epitaxy with a cavity structure mandates stringent process requirements for good selectivity, and suffers from poor process control. U.S. Pat. Nos. 5,523,606 to Yamazaki and 5,620,908 to Inoh, et al. are some examples of prior art selective epitaxy processes.
As mentioned above, CMP can be applied to form a raised extrinsic base. U.S. Pat. No. 5,015,594 to Chu et al. discloses the formation of extrinsic base polysilicon by CMP. The isolation, which is achieved by thermal oxidation, is not feasible in high performance devices due to the high temperature thermal process.
U.S. Pat. No. 6,492,238 to Ahlgren, et al. provides a self-aligned process for forming a bipolar transistor with a raised extrinsic base, an emitter, and a collector integrated with a complementary metal oxide semiconductor (CMOS) circuit with a gate. An intermediate semiconductor structure is provided having a CMOS area and a bipolar area. An intrinsic base layer is provided in the bipolar area. A base oxide is formed across, and a sacrificial emitter stack of silicon layer is deposited on both the CMOS and bipolar areas. A photoresist is applied to protect the bipolar area and the structure is etched to remove the emitter stack silicon layer from the CMOS area only such that the top surface of the emitter stack silicon layer on the bipolar area is substantially flush with the top surface of the CMOS area. Finally, a polish stop layer is deposited having a substantially flat top surface across both the CMOS and bipolar areas suitable for subsequent chemical-mechanical polishing (CMP).
Despite being capable of forming an HBT having a raised extrinsic base, the self-aligned-CMP process disclosed in the ""238 patent is complicated requiring many different processing steps to achieve the desired structure. As such, there still exists a need for providing a simple and reliable method for fabricating high-performance HBTs that have a raised extrinsic base.
One object of the present invention is to provide a simple, yet reliable method of fabricating a high-performance HBT in an integrated BiCMOS process.
A further object of the present invention is to provide a method of fabricating a HBT having a raised extrinsic base.
A still further object of the present invention is to provide a method of fabricating a high-speed HBT having a raised extrinsic base in which unity current gain frequency fT and unity unilateral power gain frequency fmax can reach 200 GHz or greater.
A yet further object of the present invention is to provide a method of fabricating an npn transistor in a BiCMOS process flow.
A still yet other object of the present invention is to provide a method of fabricating a HBT in which the reliability of the transistor is improved by reducing the leakage between the emitter region and the base region.
These and other objects and advantages are achieved in the present invention by providing and utilizing a patterned emitter landing pad stack in a non-self-aligned process. The patterned emitter landing pad stack of the present invention comprises polySi and/or SiN located atop an oxide. In the case when a combination of polySi and SiN is employed, the polySi is located atop the SiN. The patterned emitter landing pad stack which is located atop the base region serves the following three functions in the present invention: First, the patterned emitter landing pad stack aides in improving the alignment for the emitter-opening lithography. Secondly, the patterned emitter landing pad stack acts as an etch stop layer for the emitter opening etch. Thirdly, non-removed portions of the patterned emitter landing pad stack at the end of the process provides isolation between the emitter region and the raised extrinsic base region, together with the isolation spacers to be described later.
One aspect of the present invention is directed to a method of fabricating a high-performance HBT having a raised extrinsic base which includes the steps of:
forming a patterned emitter landing pad stack atop portions of a base region, said patterned emitter landing pad stack comprising at least a bottom oxide;
forming a doped semiconducting layer atop the patterned emitter landing pad stack as well as atop portions of the base region that does not contain said patterned emitter landing pad stack;
forming a material stack atop the doped semiconducting layer;
providing an emitter opening in portions of said material stack and said doped semiconducting layer stopping on an upper surface of said bottom oxide of said patterned emitter landing pad stack;
removing portions of said bottom oxide of said patterned emitter landing pad exposing a portion of said base region; and
forming an emitter in said opening.
In a preferred embodiment of the present invention, the exposed portions of the bottom oxide are removed utilizing an etching method such as a chemical oxide removal process in which minimal undercut or substantially no undercut is formed beneath the patterned emitter landing pad stack.
In the present invention, the base region includes a monocrystalline region that is surrounded on either side by adjoining polycrystalline regions. The monocrystalline region is formed atop a Si substrate, whereas the polycrystalline regions are located atop trench isolation regions that are located in the Si substrate. The raised extrinsic base of the present invention includes the doped semiconducting layer that is located above the polycrystalline regions of the base region. Because of the presence of a monocrystalline region in the base region, there is no interface formed between that portion of the base region and the intrinsic base that is formed under the emitter opening. As such, the link resistance between these two regions is very low in the HBT of the present invention.
Another aspect of the present invention relates to a structure which comprises
a base region having a monocrystalline region located atop a Si substrate and polycrystalline regions located atop trench isolation regions that are present in the Si substrate, with said monocrystalline region separating the polycrystalline regions;
a raised extrinsic base located atop the polycrystalline regions of the structure and part of the monocrystalline region that does not contain a patterned emitter landing pad stack;
an emitter opening located above said monocrystalline region, said emitter opening is defined by said patterned emitter landing pad stack; and
an emitter region located in said emitter opening.